India is setting its sights on manufacturing 3-nanometre and eventually 2-nanometre chips by the early 2030s as part of the next phase of its semiconductor push, Ashwini Vaishnaw, Minister for Electronics and Information Technology, stated while interacting with startups supported under the Design Linked Incentive (DLI) scheme.

Outlining the government’s long-term roadmap, Vaishnaw said that by 2029, India would have the capability to design and manufacture chips used in nearly 70–75% of domestic applications. “The next milestone should come by 2032, when we reach 3-nanometre chip manufacturing,” he said.

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He added that the journey towards advanced nodes such as 3 nm and 2 nm would form a central pillar of the upcoming Semicon 2.0 programme, drawing lessons from how countries like South Korea, Taiwan and Japan built their semiconductor ecosystems over decades.

Speaking at the event showcasing startups under DLI 1.0, Vaishnaw said the government’s initial approach—providing access to electronic design automation (EDA) tools, intellectual property (IP) cores and multi-project wafer (MPW) support—had been validated by tangible progress on the ground.

“Many of you have already taped out and validated your products. Several have also found markets,” he told startup founders.

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India currently has 24 startups supported under the DLI scheme, and the next phase aims to scale this number to at least 50 fabless semiconductor companies.

Under DLI 2.0, which will be integrated into Semicon 2.0, government support will be focused on six core chip categories: compute, radio frequency (RF), networking, power management, sensors and memory. “With these six, we can build any major system—whether for defence, missiles, railways or automobiles,” Vaishnaw said.

The minister also said that tape-out facilities for mature nodes such as 180 nm would be anchored at the Semiconductor Laboratory (SCL) in Mohali, while advanced nodes down to 28 nm would be supported through the upcoming Tata semiconductor fab in Dholera.

Inputs from startups under DLI 1.0, he noted, would directly shape the design of the next scheme, including decisions on areas that merit continued support and those that do not.

At the event, several founders flagged the need for stronger backing for analog and RF intellectual property, preferential market access in strategic sectors, and support to bridge costs until production volumes scale up.

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Startups showcased chips that are already in tape-out or testing stages across AI, RF and broadband applications.

Trivandrum-based Netra Semiconductor said its A2000 AI application processor taped out on TSMC’s 12 nm node in October and is currently undergoing silicon testing, while its R1000 AI-MCU is expected to tape out next month.

RF IC startup Fermionix highlighted demand from defence and satellite communications customers for its X-band radar chips and sought government support to expand into Ku- and Ka-band offerings. InCore Semiconductor, founded by members of the team behind IIT Madras’ SHAKTI processor, reiterated its focus on RISC-V-based solutions and called for preferential market access in critical sectors.

Vaishnaw also announced that the government will institute Deep Tech Awards starting in 2026, spanning sectors such as semiconductors, artificial intelligence, space and biotechnology. “With Semicon 2.0, a major part of the programme will be dedicated to achieving the 3 nm and 2 nm goals. By 2035, India should be among the top four semiconductor nations globally,” he said.